The invention relates to extracting process parameters.
For purposes of predicting the performance and characteristics of an integrated circuit, it is often desirable to measure certain parameters (called process parameters) that characterize the fabrication process that was used to fabricate the integrated circuit. Such parameters may indicate, for example, the influence that is exerted by the drain-depletion regions of n-channel and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) on the respective channels of these devices. The degree to which the channel of a particular MOSFET is influenced by its drain-depletion region is a measure of the strength and thus, the performance of the MOSFET.
For purposes of measuring, or extracting, process parameters from a particular silicon wafer, conventionally, test circuits, or structures, may be embedded in scribe lines that are located between the semiconductor dies in the wafer. Due to this arrangement, probes may be used to perform analog testing before the dies are cut and packaged to form the individual semiconductor packages, or chips. These test structures typically are destroyed in the cutting process. Because of time constraints, only structures between select dies may be tested.
Unfortunately, process parameters may vary across the wafer, and thus, the above-described analog testing techniques that are used before packaging may not be accurate enough to extract process parameters from particular dies. Furthermore, even if test structures are fabricated in a particular die, the die may not be able to be tested after packaging unless additional external pins are provided for purposes of performing the analog testing.
Thus, there is a continuing need for an arrangement and technique to address one or more of the problems that are stated above.